In general, in a double data rate synchronous dynamic random access memory (DDR SDRAM), rising and falling edges of a clock signal are used when reading data out of cells or writing data in cells.
However, when reading data out of cells, there occurs discrepancy between the first one of read data and a data strobe signal.
Referring to FIG. 1, there is provided a block diagram showing the conventional read data control.
In FIG. 1, a pipe latch unit 110 is a device for storing and maintaining data during the column address strobe(CAS) latency (CL) when data of global input/output (I/O) lines GIO<0, 1, . . . , N> are transferred to a data output driver unit 160. The CL means an interval between a first rising edge of an introduction clock and that of a data strobe signal and the data strobe signal is enabled so as to capture data. In case of a DDR SDRAM, each pipe latch employs an even latch and an odd latch.
A pipe in counter 120 sequentially generates pipe latch input control signals pin<0, 1, . . . , M>, which are used to make the data of the global I/O lines GIO<0, 1, . . . , N> sequentially inputted into the pipe latch unit 110.
An even pipe output counter 130 sequentially produces pipe latch rising output control signals rpout<0, 1, . . . , M>, which are used to transfer the data stored in the even latch sequentially into the data output driver unit 160 after the CL based on a DLL rising clock rclk_dll.
An odd pipe output counter 140 sequentially generates pipe latch falling output control signals fpout<0, 1, . . . , M>, which are used to transmit the data stored in the odd latch sequentially into the data output driver unit 160 after the CL based on a DLL falling clock fclk_dll.
A rising/falling(r/f)_divider 150 generates data control signals, which are used to alternately input the data from the even latch and the data from the odd latch to the data output driver unit 160 in response to the DLL rising clock rclk_dll and the DLL falling clock fclk_dll.
The data output driver unit 160 supplies the data provided from the pipe latch unit 110 to output pins.
A data strobe generator and driver unit 170 generates a data strobe signal QS, which is used to output read data at an edge of the data strobe signal QS when reading out data and to capture write data when writing data.
In drawings, the clock is a signal transferred through an external clock pin and used inside of a memory device. A preamble time control signal qsen_pre is a control signal used to report the start of a read operation by maintaining the data strobe signal at a low level during one clock before the first read data being outputted in the read operation. The DLL rising clock rclk_dll is a clock pulse, which is generated in a delay locked loop when an external clock is at a rising edge, and the DLL falling clock fclk_dll is a clock pulse, which is produced in the delay locked loop when the external clock is at a falling edge. A rising out enable signal routen and a falling out enable signal fouten are signals, which enable or disable the DLL rising clock and the DLL falling clock, respectively. Rising edge output control signals rclk_do_u and rclk_do_l are control signals for turning-on the data output driver unit 160 to thereby synchronize the read data with a rising edge of the external clock and output the read data. Falling edge output control signals fclk_do_u and fclk_do_l are control signals for turning-on the data output driver unit 160 to thereby synchronize the read data with a falling edge of the external clock and output the read data. Herein, “u” and “l” at the rising(falling) edge output control signals r(f)clk_do_u and r(f)clk_do_l are used to distinguish an upper part and a lower part of the data output driver unit 160 and to control the two parts separately.
For instance, if there are 16 numbers of sub output drivers in the data output driver unit 160, the control signals r(f)clk_do_u are fed to sub output drivers 0 to 7 and the control signals r(f)clk_do_l are coupled to sub output drivers 8 to 15.
Data DQ<0˜N> stored at memory cells are outputted through the data output driver unit 160 during the read operation. The data strobe signals outputted from the data strobe generator and driver unit 170 are of reporting the start of the read operation.
FIG. 3 depicts a detailed circuit diagram of the rising/falling(r/f)_divider 150 shown in FIG. 1.
The conventional r/f_divider 150 generates the rising edge output control signals rclk_do_u and rclk_do_l by logically combining the rising out enable signal routen and the DLL rising clock rclk_dll and produces the falling edge output control signals fclk_do_u and fclk_do_l by logically combining the falling out enable signal fouten and the DLL falling clock fclk_dll.
FIG. 5 is a timing diagram showing the conventional read data control.
According to the structure of FIGS. 1 and 3, in the data reading operation, the data DQ<0-N> and the data strobe signal QS(LQS/UQS) are controlled by one clock signal. However, while the first read data is transited from an output reference voltage Vddq/2, data from the second read data following the first read data are transited from a power voltage Vddq or a ground voltage Vssq. That is, a transit starting level of the first read data is different from those of the other read data. Since the first read data is always discrepant with the clock signal as much as a time that the first read data is transited from the output reference voltage Vddq/2 to the power voltage Vddq or the ground voltage Vssq, the first read data DQ(0) is outputted prior to the data strobe signal QS(LQS/UQS), so that it is impossible to perform the exact synchronization.